Overview
The NAND gate is the complement of the AND gate. It outputs LOW (0) only when all inputs are simultaneously HIGH (1). In every other input combination — including when all inputs are LOW — the output is HIGH (1). NAND stands for "NOT-AND" and its circuit symbol is simply an AND gate with an inversion bubble at the output.
The boolean expression is Y = (A · B)', or using the overbar notation: Y = A̅B̅. What makes the NAND gate special is that it is a universal gate: any boolean function — and therefore any digital circuit — can be implemented using only NAND gates. You can build NOT, AND, OR, NOR, XOR, and XNOR gates entirely from NAND gates.
This universality, combined with the fact that CMOS NAND gates require fewer transistors than AND gates (4 versus 6), makes NAND the most commonly used gate in real VLSI and IC design. The 74HC00 (quad 2-input NAND) is one of the most widely manufactured logic ICs in history.
Truth Table
| A | B | Output (Y) |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
How It Works
A 2-input CMOS NAND gate is implemented with four transistors: two NMOS transistors in series (pull-down network) and two PMOS transistors in parallel (pull-up network). This is more transistor-efficient than AND (which requires 6) and is the preferred implementation in chip design.
When any input is LOW: at least one PMOS transistor is on and the series NMOS path is broken, so the output is HIGH. When all inputs are HIGH: all NMOS transistors conduct (series path complete) and both PMOS transistors are off, pulling the output LOW.
To build other gates from NAND: NOT = NAND with both inputs tied together. AND = NAND followed by a NOT. OR = NOT each input then NAND. This is how early TTL-era designs were implemented — entire circuits from a single gate type kept the component count and stock inventory simple.
Real-World Applications
Static RAM bit cells are built from two cross-coupled NAND gates (or inverters) that hold a stable 0 or 1 state.
Flash memory uses arrays of floating-gate transistors in NAND configurations to store billions of bits on a single chip.
A SR latch built from two NAND gates debounces mechanical switches by latching the first contact and ignoring subsequent bounces.
FPGA fabrics often use NAND-based lookup tables (LUTs) to implement arbitrary logic, leveraging universality to map any function.
ALU circuits in CPUs are built almost entirely from NAND/NOR gates for area and speed efficiency in VLSI.
Try It in the Interactive Simulator
Build NAND Gate circuits in real time — drag gates, connect wires, toggle inputs, and see outputs update instantly.
Frequently Asked Questions
- Why is NAND called a universal gate?
Because you can build any other logic gate — and therefore any digital circuit — using only NAND gates. NOT = NAND(A,A). AND = NOT(NAND(A,B)). OR = NAND(NOT(A), NOT(B)). This universality means NAND alone is logically complete.
- What is the truth table for NAND gate?
The 2-input NAND truth table: (0,0)→1, (0,1)→1, (1,0)→1, (1,1)→0. The only LOW output occurs when all inputs are HIGH.
- How does NAND differ from AND?
NAND is the complement (inverse) of AND. Where AND outputs 0 for (0,0), (0,1), (1,0), NAND outputs 1 for those same inputs. And where AND outputs 1 for (1,1), NAND outputs 0.
- How many transistors does NAND use?
A 2-input CMOS NAND gate uses 4 transistors (2 NMOS in series + 2 PMOS in parallel). This is fewer than an AND gate (6 transistors), making NAND more area-efficient in chip design.
- What IC contains NAND gates?
The 74HC00 (CMOS) and 74LS00 (TTL) are classic quad 2-input NAND gate ICs. The 74HC10 provides triple 3-input NAND gates.