Overview
The NOR gate is the complement of the OR gate. It outputs HIGH (1) only when ALL of its inputs are LOW (0). If any input is HIGH, the output is LOW. NOR stands for "NOT-OR," and its symbol is an OR gate with an inversion bubble at the output.
The boolean expression is Y = (A + B)', read "NOT of A OR B." Like the NAND gate, NOR is a universal gate — any digital logic function can be implemented using only NOR gates. This makes it theoretically equivalent to NAND in expressive power, though the two differ in how other gates are constructed from them.
NOR gates are the foundation of NOR flash memory (an alternative to NAND flash with faster read times), SR latches, and certain FPGA cell architectures. The 74HC02 is the standard quad 2-input NOR gate IC.
Truth Table
| A | B | Output (Y) |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
How It Works
A 2-input CMOS NOR gate uses four transistors: two PMOS in series (pull-up) and two NMOS in parallel (pull-down). This is the complementary structure to the NAND gate.
When all inputs are LOW: both PMOS transistors conduct (series path complete), pulling the output HIGH, while both NMOS transistors are off. When any input is HIGH: at least one PMOS is off (breaking the pull-up path) and at least one NMOS is on (pulling the output LOW).
To construct other gates using only NOR: NOT = NOR(A,A). OR = NOT(NOR(A,B)) = NOR(NOR(A,B), NOR(A,B)). AND = NOR(NOT(A), NOT(B)). A NOR SR latch built from two cross-coupled NOR gates is one of the simplest bistable memory elements.
Real-World Applications
Two cross-coupled NOR gates form an SR latch — the most elementary form of memory. Set/Reset inputs control the stored state.
NOR flash uses cells in a NOR configuration, enabling random byte-addressable reads — preferred for code storage in embedded systems.
In certain bus protocols, multiple NOR gates drive a shared line, implementing distributed OR logic without extra hardware.
Logic synthesis tools can optimise circuits using only NOR gates, important for technologies where NOR is the primitive cell.
NOR gates efficiently detect when all bits of a word are zero — a common operation in condition code generation in CPUs.
Try It in the Interactive Simulator
Build NOR Gate circuits in real time — drag gates, connect wires, toggle inputs, and see outputs update instantly.
Frequently Asked Questions
- What is a NOR gate?
A NOR gate outputs 1 only when all inputs are 0. It is the complement of OR: Y = (A + B)'. If any input is 1, the output is 0.
- Is NOR gate universal?
Yes. NOR is a universal gate — any boolean function can be built from NOR gates alone. NOT = NOR(A,A). OR = NOR(NOR(A,B), NOR(A,B)). AND = NOR(NOR(A,A), NOR(B,B)).
- What is the difference between NOR and NAND?
Both are universal gates, but their truth tables differ. NAND outputs 0 only when all inputs are 1. NOR outputs 1 only when all inputs are 0. They are complements of AND and OR respectively.
- How does a NOR latch work?
A NOR SR latch has two NOR gates with cross-coupled outputs. When S=1, R=0: the latch is Set (Q=1). When S=0, R=1: Reset (Q=0). When S=0, R=0: the latch holds its previous state. S=R=1 is the forbidden state.
- What is the IC for NOR gate?
The 74HC02 (CMOS) and 74LS02 (TTL) provide four 2-input NOR gates in a single package.