Overview
The half adder is the simplest binary addition circuit. It takes two 1-bit inputs (A and B) and produces two outputs: a Sum bit and a Carry bit. It is called a "half" adder because it does not accept a carry-in from a previous stage — making it useful only for the least significant bit of a multi-bit addition.
Despite its simplicity, the half adder demonstrates a crucial concept: binary arithmetic can be implemented entirely using logic gates. The Sum output is computed by an XOR gate (recall that XOR gives 1 when inputs differ, matching the single-bit sum 1+0=1 or 0+1=1, but giving 0 for 1+1=10). The Carry output is computed by an AND gate (carry occurs only when both inputs are 1).
The half adder consists of just two gates: one XOR gate for the Sum and one AND gate for the Carry. This minimal circuit directly illustrates the connection between boolean algebra and digital arithmetic.
Truth Table
| A | B | Sum (S) | Carry (C) |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
How It Works
Half adder equations: Sum = A ⊕ B (XOR gate) Carry = A · B (AND gate)
The XOR gate computes the sum because XOR gives 1 only when inputs differ — matching single-bit addition: 0+0=0, 0+1=1, 1+0=1, and 1+1 produces sum 0 (with carry). The AND gate computes the carry because carry is only generated when both inputs are 1.
The half adder's limitation is that it cannot accept a carry-in from a previous stage. For adding bits beyond the least significant position, you need a full adder. A full adder is built from two half adders plus an OR gate for the carry: HA1 adds A and B, HA2 adds the HA1 sum with Carry-In, and an OR gate merges the two carry outputs.
Real-World Applications
The half adder handles the rightmost bit in a multi-bit ripple-carry adder, where no carry-in exists.
Adding 1 to a register (incrementing) starts with a half adder at the LSB, showing the carry effect upward through the number.
Two half adders plus an OR gate form one full adder — demonstrating hierarchical circuit design from simple to complex.
The half adder is the standard first example of combinational arithmetic in digital logic coursework worldwide.
Try It in the Interactive Simulator
Build Half Adder circuits in real time — drag gates, connect wires, toggle inputs, and see outputs update instantly.
Frequently Asked Questions
- What is a half adder?
A half adder adds two 1-bit binary inputs (A and B) and produces a Sum (A ⊕ B) and a Carry (A · B). It cannot accept a carry-in, which is why it is called "half" — it needs to be combined with another half adder to form a full adder.
- What gates make up a half adder?
A half adder uses one XOR gate (for the Sum) and one AND gate (for the Carry). That is the minimum — just two gates.
- What is the difference between a half adder and a full adder?
A half adder has 2 inputs (A, B) and 2 outputs (Sum, Carry). A full adder has 3 inputs (A, B, Carry-In) and 2 outputs (Sum, Carry-Out). Full adders can be chained for multi-bit addition.
- What is the half adder truth table?
Four rows: (0,0)→Sum=0, Carry=0; (0,1)→Sum=1, Carry=0; (1,0)→Sum=1, Carry=0; (1,1)→Sum=0, Carry=1.
- Why does 1+1 give Sum=0 in a half adder?
In binary, 1+1=10 (decimal 2). The half adder captures only the Sum bit (the LSB), which is 0. The Carry=1 represents the second bit that would carry to the next position.