Overview
The NOT gate — also called an inverter — is the simplest of all logic gates. It has exactly one input and one output. Its sole function is to produce the logical complement of the input: a HIGH input (1) produces a LOW output (0), and a LOW input produces a HIGH output. The NOT gate literally "inverts" or "flips" the binary signal.
The boolean expression for a NOT gate is Y = A' (read "A prime" or "not A"), also written Ā (A with an overbar). In circuit diagrams, the NOT gate is drawn as a triangle with a small bubble (inversion circle) at the output. This bubble notation is used wherever inversion occurs in logic diagrams.
Despite its simplicity, the NOT gate is indispensable. It appears as the "bubble" half of NAND and NOR gates, is essential for creating complementary signals, and forms the backbone of signal level conversion and clock inversion in synchronous circuits. A single CMOS inverter is the smallest CMOS logic cell, requiring just two transistors.
Truth Table
| A | Output (Y) |
|---|---|
| 0 | 1 |
| 1 | 0 |
How It Works
A CMOS inverter consists of one PMOS transistor connected to the supply voltage (VDD) and one NMOS transistor connected to ground (VSS), with their gates tied to the input and their drains tied together as the output.
When the input is LOW (0): the NMOS transistor is off and the PMOS transistor is on, connecting the output to VDD → output is HIGH (1). When the input is HIGH (1): the NMOS transistor is on and the PMOS transistor is off, connecting the output to VSS → output is LOW (0).
This is the fundamental CMOS inverter — only two transistors, complementary switching, and near-zero static power consumption. It is the basis of every more complex CMOS gate.
Real-World Applications
Many circuits need both a signal and its complement. An inverter creates the complement from a single source.
Flip-flops often need both the rising and falling clock edges. An inverter on the clock line provides both phases.
By De Morgan's theorem, NOT gates let you convert between AND/OR forms and NAND/NOR forms, enabling gate-level optimisation.
Active-LOW signals (common in older TTL ICs) are inverted by NOT gates to match active-HIGH logic in modern systems.
An odd number of inverters connected in a ring oscillate, forming the simplest possible oscillator circuit used in timing tests.
Try It in the Interactive Simulator
Build NOT Gate (Inverter) circuits in real time — drag gates, connect wires, toggle inputs, and see outputs update instantly.
Frequently Asked Questions
- What does a NOT gate do?
A NOT gate inverts its input. If the input is 1, the output is 0. If the input is 0, the output is 1. It implements logical negation: Y = A'.
- How many inputs does a NOT gate have?
A NOT gate always has exactly one input and one output. Gates with two or more inputs cannot be simple inverters.
- Why is NOT gate also called an inverter?
Because it inverts the logic level of the signal. The term "inverter" emphasises the function (flipping the signal) rather than the logical operation (NOT).
- Can you build a NOT gate from a NAND gate?
Yes. Connecting both inputs of a NAND gate to the same signal produces Y = (A · A)' = A'. A NAND gate with tied inputs is functionally identical to a NOT gate.
- How many transistors does a NOT gate use?
A CMOS NOT gate (inverter) uses only 2 transistors — one PMOS and one NMOS. It is the smallest possible CMOS logic cell.